Posts by DJ0VL

    I am sure he knows. I will ask next time. The reasons for these errors are probably interesting and subtle.


    Thank you for this highly interesting paper. Figure 4 confirms my observations regarding the short term stability. I commented on this as the observed stability may be normal behaviour for the type of GPDSO used, however it seems somewhat higher than the stated and measured stability data for this GPSDO.

    I'm fully aware that we are discussing deviations on a very high level, nevertheless I'm interested in knowing the reason for the errors. We do not know whether its all due to the stability of the GPSDO, but imho a decent GPSDO has a significantly higher stability.

    Allan deviation is stability.. 130Hz in 10 GHz is accuracy. Check here for a good explanation of the subject.

    That said, there are numerous explanations for this offset including hw failures. Maybe telling the WebSDR team directly?

    Thanks for the link and of course you are right. I'm familiar with the difference between stability and accuracy, my comment referred to the noticeable jitter. Sorry for the unclear wording.

    73 Jean

    PS: I would like to tell the team directly, but finding a contact address on the webpage is not easy.

    Hi all,

    Half a year later, the issue remains unchanged. The Goonhilly WebSDR now seems to be off by around 130Hz. Apart from the offset, there is a visible jitter of quite a few Hz.

    The screenshot below shows the same audio signal as received simultaneously by the Brazil WebSDR (trace at the left side), the Goonhilly WebSDR (trace at the right side) and by my own receiver (trace at 762Hz).

    The Brazil WebSDR ( is shown just for comparison as Thomas mentioned it above and I guess it uses a simple TCXO as a reference. Both offset and drift are heavily dependent on the time of day.

    73 Jean DJ0VL


    C123 and C124 form a capacitive voltage divider to adapt the ~1.8Vpp output level of the original Pluto oscillator to the 1.3Vpp required by the AD9363.

    The XTALN input of the AD9363 has an input resistance of about 10kOhm in parallel with 10pF, so that the capacitance of the input pin is sufficient to form the voltage divider with C123. Therefore C124 is not placed on the PCB.

    73 Jean


    The Si5351 is able to generate a quite clean 25MHz signal if you consider some basic requirements:

    - you need a clean 10MHz input signal.

    - the Si5351 is sensitive to supply voltage noise. Use linear voltage regulators and low esr decoupling caps.

    - most important: use even integer divider ratios, as well for the pll stage as for the multisynth divider.

    Usage of even integer divider ratios is essential for a clean output signal, a fractional-n divider leads to a messy signal with lots of spurs.

    The output signal is a square wave, so you may want to add some low-pass filtering.

    73 Jean