Posts by DB8DT


    Details about the input resistance of the SDR chip can be found in the reference manual (-> page 15).

    In short: you can't assume a 50 Ohms load.

    As mentioned in one of my last articles above, you could build a voltage divider (C123/C124) or use an external coax attenuator, as others have suggested.

    Here's another possible solution:

    According to the schematic you could also install C124 (which is in the unmodified Pluto not installed) with a value of 18 to 27pF and keep the existing 18pF series capacitor (C123).

    In combination with the capacitance of the XTALN input (approx 10pF) they would form a capacitive voltage divider like this:

    approx. 1.3 to 1.1Vpp @ XTALN

    In case if you would like to reinstall the org. TCXO you only have to remove C124.

    Got all the things together and was able to do some tests with the 74LVC1G04GV inverter.

    I could achieve an output of about 1.3 Vpp with the following circuit design:

    Now all the problems I had with Pluto after changing the TCXO are gone. No more drift and no spurious signals.

    I have some inverters left just in case someone wants to try this solution.

    I also have problems that seem to be caused by a 1.8V Abracon TCXO and it's low clock signal. I had an idea similar to PY1SAN, and my plan is to translate the cropped sine wave from the TCXO to a 1.8V CMOS signal.

    After some searching I found an inverter from Nexperia (74LVC1G04GV) and I decided to give it a try. It seems the specs are nearly the same as the one from TI.

    With some luck I will getting tomorrow the ordered parts, and then I can do some tests over the weekend.