Hi,

your order is ok. Wilhelm is right, the flap is a capacitor and must not touch the helix. Try to bend it back to the original position.

Good luck!

Detlev

Hi,

that isn't a problem of the pigtail, it is a problem of the solder connection of two cables. even a N-type right-angled plug-jack adaptor isn't ideal:

Detlev

Hi,

2.4 GHz is not DC, you can't solder two cables together!!!!

You have to use the appropriate connectors for your Ultraflex 7 cable, SMA and N for the Helix.

73 Detlev, DC7KG

Hi,

you have to use connectors on your Ultraflex 7 cable, you can't solder pigtails together.

Detlev

Which type of connector do you use on the Ultraflex 7? There are SMA connectors for that cable.

Detlev

I don't understand the pigtail. You should use a N-connector on your ultraflex 7 cable and a N-connector at the helix.

Detlev

Hi,

the Helix has the right polarization. You should use a N-connector socket and an approriate cable.

Detlev

Hi,

that is the theoretical value, don't forget the additional noise of the multiplier/divider.

Nevertheless AD recommends 80 MHz for the Pluto, you have 4 different choises: 40 MHz x 2, 80 MHz x 1, 160 MHz :2, 320 MHz :4.

73 Detlev

Quote from DD1US

I do not know the internals of the ADI-IC AD9361 and thus I cannot judge how much of a difference with respect to the phase noise a reference clock of 40 MHz versus 50 MHz creates. Did you evaluate/measure this ?

Regards

Matthias

http://www.dd1us.de

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Hi Matthias,

it is not the difference between 40 and 50 MHz, it is the difference between 80 (40 x 2) and 50 Mhz.

Because I have no 50 MHz clock I can't measure it, but I believe AD knows the facts.

73 Detlev

Hi,

the AD document UG-570 says, that the scaled frequency should be as close to 80 MHz as possible, i.e. 40 MHz x 2. But you can't take 50 MHz x 1.6!

Detlev

REFERENCE CLOCK SETUP AND OPERATION

If the DCXO is not used, an external reference clock needs to be ac-coupled to XTALN (Pin M12). XTALP (Pin M11) is not connected (leave floating). The clock frequency must be between 5 MHz and 320 MHz, and can be scaled by 1×, ½×, ¼× and 2× using BBPLL, Rx and Tx reference dividers. The valid frequency range for the RFPLL phase detectors is 10 MHz to 80 MHz, and the scaled frequency of the reference clock must be within this range. For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible. The selection between DCXO and external reference clock is made in the ad9361_init function.

Quote from SV8QG

Has anybody used this TCXO for 10 MHZ and 40 MHZ ?

https://www.ebay.co.uk/itm/10M…id=p2047675.c100752.m1982

Hello,

here are the spectra with the internal clock, the OSC101 (40MHz) and an RTL 203004 (TCXO 40 MHz).

73 Detlev, DC7KG

Hi,

I suppose you get more phase noise, look at the spectra in this post. I'll try to measure it.

73 Detlev, DC7KG

AD says in UG 570: For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible.

The transmission spectrum at 2.4 GHz is decisive.

73 Detlev, DC7KG

Hi,

AD recommends 80 MHz (40 MHz x 2) in document UG570:

REFERENCE CLOCK SETUP AND OPERATION

If the DCXO is not used, an external reference clock needs to be ac-coupled to XTALN (Pin M12). XTALP (Pin M11) is not connected (leave floating). The clock frequency must be between 5 MHz and 320 MHz, and can be scaled by 1×, ½×, ¼× and 2× using BBPLL, Rx and Tx reference dividers. The valid frequency range for the RFPLL phase detectors is 10 MHz to 80 MHz, and the scaled frequency of the reference clock must be within this range. For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible. The selection between DCXO and external reference clock is made in the ad9361_init function.

The level for the clock should be 1.3 V p-p maximum(lower swings can be used but will limit performance). This signal can be a clipped sine wave or a CMOS signal. The best performance will be seen with the highest slew rate possible.

The XTALN (Pin M12) has an input resistance of ~ 10 kΩ in parallel with 10 pF.

PHASE NOISE SPECIFICATION

The AD9361 Rx and Tx RFPLLs use the DCXO or external clock as their reference clock as well. For this reason, it is extremely critical that the crystal or clock source have very low phase noise. The recommended phase noise specification is shown in Figure 2.

73 Detlev, DC7KG

I don't want -90 dBc/Hz, AD demands it in UG570, look at the diagram.

73 Detlev, DC7KG

Hi André,

AD requests more than 90 dB, see page 1. Have you looked at the transmit spectrum with a spectrum analyzer? The Chinese 40 MHz OCXO and the KVG TCXO produce unusable transmit spectra.

73 Detlev, DC7KG

Hi,

AD requires a low-noise clock, Murata does not provide any information about it

Regards Detlev, DC7KG

Hi André,

I think the phase noise is more important than the frequency stability, see images on page 1. What about the noise of the Si5351?

73 Detlev, DC7KG

Hi,

Also the TCXO from KVG (40 MHz, RTL 203004) is unusable.

Compare the image with the images above.

73 Detlev

Hallo Frank,

beim Senden erreicht mein Signal den Pegel der CW Bake. Wie hoch ist denn Deines?

73 Detlev, DC7KG