External Clock for Adalm Pluto

  • IK1IYU recently mentioned, that it


    "Looks like the easiest pluto sdr tcxo removal….is NOT removing it at all. According to Analog Device Pluto schematics, pin 1 of the tcxo is an Enable/Disable pin and simply grounding it should disable it."

    TCXO for Pluto

    But if pin 1 is not connected statically to GND, an automatic clock selection can be realized with little effort.

    This is made possible by TI's SN74LVC1G125 chip, which has a low-active enable input and accepts input signals up to 5V with 1.8V VCC. So a single Si-npn transistor provides automatic source switching, a pull-up resistor is not necessary.

    The tested circuit diagram is attached.

    The advantages are:

    The original XO does not have to be removed.

    The Pluto still works even if no external clock is fed in.

    And last but not least, accidentally too high Clk levels or ESD no longer directly endanger the heart of Pluto.

  • Now the practical part.

    For the test the circuit was simply soldered together, quick and dirty, without a printed circuit board.

    U1 and the Pluto-XO are almost pin-compatible. However, the metal housing of Y3 prevents a simple piggyback mounting.

    The transistor Q1 is placed upside down, with the emitter at C121. R1 consists of five parallel-connected 1k resistors, because they were just available.

    A level of about 6.5dBm is just enough to switch to external clock at the given impedance ratio of the input transformer. At more than 12 dBm, however, U1 is increasingly overdriven.

    With this circuit the Pluto was able to operate with external clock frequencies between 20 and 50 MHz. 10 MHz unfortunately did not work.

    The currently applied clock frequency (in the example 25 MHz) must be submitted to the Pluto with the following well known commands:

    fw_setenv ad936x_ext_refclk "<25000000>"

    fw_setenv xo_correction 25000000

    pluto_reboot reset

  • IK1IYU

    Hi Piero,

    the main reason for the input transformer is to avoid a ground loop, which can cause problems such as increased phase noise and spurious signals. Besides, one gains a degree of freedom for the adjustment to the output level of the used external OCXO or GPSDO.

    If the switching threshold of SN74LVC1G125 is assumed to be 0.9V and its input protection diode conducts from 0.5V, you get about 2*(0.5+0.9)=2.8Vpp as optimal input voltage for the chip. This applies at least for sinusoidal driving to achieve about 50% duty cycle at the output. A different transformation ratio obviously requires a correspondingly adjusted value for R1. Placing R1 on the secondary winding of the (non-ideal) transformer reduces overshoot when the input signal is square wave.

    The transformer is certainly not the cause of the 10 MHZ problem. In the ADI forums it is reported that at this frequency a sine wave with 1Vpp at the AD936x clock input is mandatory. The SN74LVC1G125 simply cannot do this.

    But for us 25MHz are much more interesting anyway, because they are also needed for the LNB.

    vy 73,


  • DM5RM

    Hi Roland

    Thanks for providing this design. I am going to try building it for my Pluto on a small PCB. I have found an SMT transformer that I think will work: Coilcraft WBC4-1TLB

    I have a question about your schematic. The transformer primary is shown floating but in the photo of your test, it looks like the primary is grounded through the solder tag. Does this make a difference?

    Thanks and 73
    Ray M0DHP

  • M0DHP

    Hi Ray

    Sorry, your question is quite valid.

    To avoid ground loops it is obviously better if the transformer is not grounded on the primary side.

    I just needed a mechanical strain relief for my quick-and-dirty setup.

    The Coilcraft transformer you have found seems to be a good choice.

    73 Roland

  • Folks,
    I did:

    fw_setenv ad936x_ext_refclk "<25000000>"

    fw_setenv xo_correction 25000000

    pluto_reboot reset

    and now pluto does not receive. Does work but it doses not receive. Perhaps the external clock level is too low.

    How can I revert these commands above?

    73 de Béla