Where can I buy a TCXO

Hi,

Also the TCXO from KVG (40 MHz, RTL 203004) is unusable.

Compare the image with the images above.

73 Detlev

Hi,

Please, could you suggest a good replacement TCXO chip which is available in EU e.g at digikey, mouser or any other shops?

Thanks

73 DX

Kornel

Hi André,

I think the phase noise is more important than the frequency stability, see images on page 1. What about the noise of the Si5351?

73 Detlev, DC7KG

Let me share that I found this alternative in a blog, but also out of stock: MURATA XNCLH40M000THJA1P0

Any other alternative do you aware of? I'd like to avoid buying a GPSDO...

Hi,

AD requires a low-noise clock, Murata does not provide any information about it

Regards Detlev, DC7KG

I use the ASTX TCXO 40 MHz 0,5ppm in several Pluto

(TCXO 40MHz, 1,8V ASTX-13-C-40.000Mhz-I05T 0,5ppm)

Phase noise is and was never a problem.

73 de Robert

Hi André,

AD requests more than 90 dB, see page 1. Have you looked at the transmit spectrum with a spectrum analyzer? The Chinese 40 MHz OCXO and the KVG TCXO produce unusable transmit spectra.

73 Detlev, DC7KG

Quote from DC7KG

Hi,

UG570 says:

The AD9361 Rx and Tx RFPLLs use the DCXO or external clock as their reference clock as well. For this reason, it is extremely critical that the crystal or clock source have very low phase noise. The recommended phase noise specification is shown in Figure 2.

73 Detlev

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When you specify phase noise, at what offset frequency do you want the -90dBc/Hz?

I don't want -90 dBc/Hz, AD demands it in UG570, look at the diagram.

73 Detlev, DC7KG

the attached .pdf is the page with the "PHASE NOISE SPECIFICATION" DC7KG is talking about (taken from the AD UG-570 doc: ez.analog.com/cfs-file/__key/telligent-evolution-components-attachments/00-441-00-00-00-07-91-97/AD9361_5F00_Reference_5F00_Manual_5F00_UG_2D00_570.pdf ).

it will be quite difficult to find a TCXO or an OCXO with those specs.

that's probably the reason why AD engineers chose a crystal oscillator???

BTW I found this one by ABRACON: AST3TQ-40.000MHZ-5.

unfortunately it seems no longer in production and, more over, it's quite expensive: some 50€...

TG2520SMN TCXO

This seems to be a good candidate : https://hu.mouser.com/datashee…MN_en_1649545-1889946.pdf

Phase noise figures :https://www5.epsondevice.com/j…al_info/pdf/pb_m_tcxo.pdf

0.5ppm version available and the price is around 2 USD at digikey

What is your opinion?

HG0NCL I'm also looking at this, but they seem not to be in stock either in Digikey or Mouser. However, I found a supplier that claims to have them in stock in China. I'll talk to him and maybe buy some samples for cheap https://www.alibaba.com/produc…llator_1600201492795.html

40MHz seems to be out of stock but 25Mhz, and some other variants are available. As I read the Pluto docs, internal clk sours can be any value between 19 and 50Mhz should work as long as adjust the actual freq in the boot config.

Hi,

AD recommends 80 MHz (40 MHz x 2) in document UG570:

REFERENCE CLOCK SETUP AND OPERATION

If the DCXO is not used, an external reference clock needs to be ac-coupled to XTALN (Pin M12). XTALP (Pin M11) is not connected (leave floating). The clock frequency must be between 5 MHz and 320 MHz, and can be scaled by 1×, ½×, ¼× and 2× using BBPLL, Rx and Tx reference dividers. The valid frequency range for the RFPLL phase detectors is 10 MHz to 80 MHz, and the scaled frequency of the reference clock must be within this range. For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible. The selection between DCXO and external reference clock is made in the ad9361_init function.

The level for the clock should be 1.3 V p-p maximum(lower swings can be used but will limit performance). This signal can be a clipped sine wave or a CMOS signal. The best performance will be seen with the highest slew rate possible.

The XTALN (Pin M12) has an input resistance of ~ 10 kΩ in parallel with 10 pF.

PHASE NOISE SPECIFICATION

The AD9361 Rx and Tx RFPLLs use the DCXO or external clock as their reference clock as well. For this reason, it is extremely critical that the crystal or clock source have very low phase noise. The recommended phase noise specification is shown in Figure 2.

73 Detlev, DC7KG

Hi,

Here someone states this: " I was able to successfully swap to a 26 MHz 0.5ppm TCXO (leftover from a previous project) without any issue"

https://ez.analog.com/adieduca…-clock-to-the-adalm-pluto

"fw_setenv ad936x_custom_refclk "<26000000>""

He's also working with 25Mhz here: https://tbspace.de/plutosdrclockinput.html

Neither is a divider of 80 Mhz I believe

AD spec says this:

80 cannot be divided by 19 or 50

So I'm still feel that any value could work. Maybe I'm wrong but how can we make sure?

AD says in UG 570: For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible.

The transmission spectrum at 2.4 GHz is decisive.

73 Detlev, DC7KG

Using non-optimal freq TCXO will cause drift or spurious signals on TX or what would be the practical effect?

Sorry for the newbie question.

Hi,

I suppose you get more phase noise, look at the spectra in this post. I'll try to measure it.

73 Detlev, DC7KG